1. Field of the Invention
The invention relates to Field Programmable gate Arrays. It relates to a configurable I/O architecture that allows user configuration of I/O modules of an FPGA.
2. Prior Art
Almost all integrated circuits (IC) use I/O buffers to connect internal circuit node to other circuits external to the IC. These I/O buffers can be Input, Output or bidirectional I/O. Further, each I/O buffer is designed to meet electrical specifications dictated by industry standards such as TTL, LVTTL, LVCMOS, GTL. It is also common for circuit designers to design each I/O buffer with multiple transistors in parallel. For example, 2 -4 P-type transistors may be connected in parallel to form the pullup section of the buffer, while 2-4 N-type transistors may connected in parallel to form the pulldown section of the buffer. Designers may then decide to use some or all of the transistors as needed by the circuit application to meet performance criteria, a particular I/O standard and noise considerations.
Selection of the transistors connected into the circuit is usually done by masking options such as metal, Vias and contacts. Further, some FPGAs have used similar techniques to select one or more transistors into the I/O buffer to provide slew control. One such FPGA that performs this function is the ACT 1280 FPGA from Actel corporation. A user may configure his I/O buffer to have either fast slew or slow slew by programming an appropriate antifuse element. This feature allow the user control over speed and noise that is induced into the circuit by the switching I/O buffers.
Another FPGA that features configurable I/O buffers is the Virtex FPGA from Xilinx corporation as described in 11/98 product specification. It features highly configurable input and output buffer which provide support for a wide variety of I/O standards. Input buffers can be configured as either a simple buffer or as a differential amplifier input. Output buffers can be configured as either a Push-Pull output or as an Open Drain output. Selection of the desired standard is done by configuration memory bits. Further, different power supplies are provided to the I/O buffer as needed by the standard.
Several FPGA architectures have been described by ElGanal in U.S. Pat. No. 4,758,745 by El-Ayat in U.S. Pat. Nos. 5,451,887; 5,477,165 and 5,570,041 and by Plants in U.S. Pat. No. 5,625,301. The embodiments described in this invention will work very well with the above inventions.